Phase locked loops (or PLLs) traditionally have been used to attempt to lock (albeit poorly) a phase of a signal to a reference phase of a reference signal by control feedback to a controllable oscillator providing the signal. However, this attempt to lock is severely hampered by jitter amplification or jitter peaking, forcing traditional PLLs to a compromised locking to an average of phases over many multiple cycles via large loop filtering. The respective location of the signal phase relative to a reference phase is established by a phase detector which outputs a signal used to shift the frequency and hence the phase of the oscillator. Phase locked loops have application in board-level communication, wireless communication (including FM demodulation), clocking schemes, and frequency synthesis in industries including radio, telecommunications, and computers, to name only a few examples.
Historically, phase detectors have been used to detect the relative locations of signal phases to reference phases from reference signals. All phase detecting methods used previously have relied on once-a-cycle sampling (discrete-time control systems) to determine whether the signal phase precedes or follows the reference phase, and then amplifying that difference via the loop to shift the signal phase in the direction of the reference phase. Due to inherent jitter peaking, amplifying the detected difference to shift the signal phase too far past the reference phase to where the loop becomes unstable, amplification thus has to be greatly reduced via loop filtering. This severely limits accuracy and leads to a low bandwidth compromise. All traditional PLLs have grappled with jitter peaking and have had to settle for far from ideal performance due to this limitation.